With the evolving of semiconductor technologies, semiconductor dies are becoming increasingly smaller. However, more functions need to be integrated into the semiconductor dies. Accordingly, the semiconductor dies need to have increasingly greater numbers of I/O pads packed into smaller areas. As a result, the packaging of the semiconductor dies becomes more difficult, which adversely affects the yield.
To allow for more solder balls connected a die, fan-out wafer level chip scale package (WLCSP) was developed. In the fan-out WLCSP, dies are sawed from wafers before they are packaged onto other wafers, and only “known-good-dies” are packaged. An advantageous feature of this packaging technology is that the I/O pads on a die can be redistributed to a greater area than the die itself, and hence the number of I/O pads packed on the surfaces of the dies can be increased.
Currently, the packages are tested using probe cards, which have probe pins that may contact the contact pads (or metal bumps, solder balls, etc.) of the devices-under-test (DUTs). The testing of the fan-out WLCSPs, however, faces challenges. For example, the fan-out WLCSPs are prone to warpage due to elevated temperatures. The warpage in the package may cause good packages being misjudged as bad package since some of the solder balls of the DUTs may not be able to be in contact with some of the probe pins during the probing. To avoid such a problem, an excess force may be applied to press the probe cards against the DUTs in order to ensure the contact between the probe cards and the DUTs. This, however, may result in the package and the probe cards being damaged.